Recently, in response to improvement of capacity expansion of memories, TFT types of load transistors have been used in SRAMs instead of high resistance types of load element, which are conventional. In a high resistance type of load system, a gate electrode, a resistance line layer and a high resistance layer are respectively formed on first, second and third layers. On the other hand, in a TFT type of load system, first and second layers are fabricated in the same manner as the high resistance type of load system, however, a TFT gate electrode and a TFT substrate region are formed on third and fourth layers, respectively.
In a conventional SRAM (Static Random Access Memory) with bottom-gate TFT load transistor described in a publication, Japanese Patent Kokai Heisei 2-295164, a pair of PMOS load transistors are formed on a pair of NMOS driver transistors and a pair of NMOS transmission transistors.
In each PMOS load transistor, a high concentration P-type impurity region to be a source-drain region is formed by photolithography technique using a photo resist. In the photolithography processing, misalignment may be happened, for example, overlapped area of a gate electrode of the transistor and the high concentration P-type impurity region varies and thereby effective channel length varies as well. By the misalignment, the pair of the PMOS load transistors are unbalanced in characteristic, so that the transistors have the different standby current values. According to the conventional memory cell, it is difficult to enlarge an area of channel regions. That is, if the channel regions are formed to be large, the memory cell itself should be large as well, which is a big problem in miniaturizing of semiconductor device.